The present invention relates to a semiconductor memory device including a number of data input/output terminals, and more particularly, to a data input/output sensing circuit for controlling a data input/output line functioning as a data bus line within a memory chip.
Generally, semiconductor memory devices include a number of data input/output lines (hereinafter referred to as DIO lines) as internal data bus lines inputting and outputting data to/from the exterior of the memory chip device. There are two types of DIO lines. One is DIO lines used in pairs and the other is the use of single DIO lines.
When using DIO lines in pairs, logic circuits as shown in FIG. 1 through FIG. 4 are used. In this case, the number of the DIO lines is twice the number of data input/output terminals (hereinafter referred to as a DQ terminal) and usually the DIO lines have been precharged to a logic "high" state.
FIG. 1 is a circuit diagram illustrating the structure of a reading driving circuit which connects data read out from a memory cell array and provided on the input/output lines IO and IOB of the memory cell to the DIO lines DIO and DIOB. FIG. 2 is a circuit diagram illustrating the structure of an output driving circuit which outputs data provided to the DIO lines DIO and DIOB through the DQ terminal DQ. The input/output line IOB is complementary to the input/output line IO, and similarly the DIO line DIOB is complementary to the data input/output line DIO.
In FIG. 1, the DIO lines DIO and DIOB are precharged with a precharge signal PRECH of the logic "low" state. Assuming that data read out from the memory cell transmitted along the input/output line IO at the logic "high" state and to the input/output line IOB at the logic "low" state, it is then input to an I/O sense-amplifier 102. If an input/output sensing enable signal IOSE is enabled to the logic "high" state, MOS field effect transistors MOSFETs 114 and 122 are turned ON and MOSFETs 116 and 120 are turned OFF, thereby continuously maintaining the line DIO at the logic "high" state and changing the line DIOB, previously precharged to the logic "high" state, to the logic "low" state. Signals on the DIO lines DIO and DIOB are respectively applied to the lines in FIG. 2, and accordingly, the line DIO of FIG. 2 goes to the logic "high" state and the line DIOB goes to the logic "low" state. Then, if a read data transmitting pulse RDTP is enabled to the logic "high" state, a MOSFET 208 is turned ON and a MOSFET 210 is turned OFF according to the logic state of the DIO lines DIO and DIOB. Consequently, data output buffer 212 outputs data of the logic "high" state through the DQ terminal to the exterior of the memory device.
FIG. 3 is a circuit diagram illustrating the structure of an input driving circuit which connects data input through the DQ terminal DQ from the exterior of the memory device to the DIO lines DIO and DIOB. FIG. 4 is a circuit diagram illustrating the structure of a writing driving circuit which applies data provided in the DIO lines DIO and DIOB to the I/O lines IO and IOB to thereby write data in the memory cell. Assuming that DQ terminal is logic "high" state, in FIG. 3, if a writing data transmitting pulse WDTP is enabled to the logic "high" state, MOSFETs 308 and 316 are turned ON and MOSFETs 310 and 341 are turned OFF, so that the line DIO goes to the logic "high" state and DIOB to the logic "low" state. Signals of the DIO lines DIO and DIOB are respectively applied to the lines in FIG. 4, and accordingly, the line DIO goes to a logic "high" state and the line DIOB goes to the logic "low" state. Thereafter, if the data transmission control pulse DTCP is enabled to the logic "high" state, the MOSFETs 408 and 416 are turned ON and MOSFETs 410 and 414 are turned OFF according to the logic state of the DIO lines DIO and DIOB. Consequently, the I/O line IO goes to the logic "high" state and the I/O line IOB thereof goes to the logic "low" state, to thus write data having a "high" state in the memory cell.
When using single DIO lines, logic circuits as shown in FIG. 5 to FIG. 8 are used. In this case, the number of DQ terminals is equal to the number of DIO lines.
FIG. 5 is a circuit diagram illustrating the structure of a reading driving circuit which connects data provided in the IO lines IO and IOB of the memory cell to the line DIO. FIG. 6 is a circuit diagram illustrating the structure of an output driving circuit which outputs data provided to the line DIO through the DQ terminal DQ. Assume that data read out from the memory cell is input to the I/O line IO at the logic "high" state and to the I/O line IOB at the logic "low" state. In FIG. 5, if the input/output sensing enable signal IOSE is enabled to the logic "high" state, MOSFET 512 is turned ON and MOSFET 514 is turned OFF, and therefore the line DIO goes to the logic "high" state. Referring to FIG. 6, after the line DIO goes to the logic "high" state, if the read data transmitting pulse RDTP is enabled to the logic "high" state, MOSFET 610 is turned ON and MOSFET 612 is turned OFF. Consequently, data output buffer 614 outputs data of the logic "high" state through the DQ terminal DQ to the exterior of the memory device.
FIG. 7 is a circuit diagram illustrating the structure of the input driving circuit which connects data input through the DQ terminal DQ from the exterior of the memory device to the DIO line DIO. FIG. 8 is a circuit diagram illustrating the structure of the writing driving circuit which applies data provided in the DIO line DIO to the I/O lines IO and IOB to thereby write data in the memory cell. Assuming that the DQ terminal DQ is at the logic "high" state, in FIG. 7, if the writing data transmitting pulse WDTP is enabled to the logic "high" state, MOSFET 710 is turned ON and MOSFET 712 is turned OFF, and therefore the line DIO goes to the logic "high" state. Referring to FIG. 8, after the DIO line DIO goes to the logic "high" state, if the data transmission control pulse DTCP is enabled to the logic "high" state MOSFETs 812 and 818 are turned ON and MOSFETs 814 and 816 are turned OFF. Consequently, the I/O line IO goes to the logic "high" state and the I/O line IOB goes to the logic "low" state to thereby write data at the logic "high" state in the memory cell.
When using DIO lines in pairs, as described above, the number of the DIO line is twice the number of DQ terminals and the DIO lines have to be precharged to the logic "high" state. However, when using a single DIO line, because the DIO line is fully swung, a sense amplifier 502 and a driving FET 512 of FIG. 5 and a driving FET 710 of FIG. 7 have to have a size larger than sense amplifier 102, driving FETs 114 and 120 of FIG. 1 and driving FETs 308 and 314 of FIG. 3, which are used when the pairs of DIO lines are precharged.
However, in the conventional circuits as described above, timing of the DIO line data transmission, a read data transmitting pulse and a data transmission controlling pulse is critical in order to prevent non-effective data from being applied to the I/O lines or DQ terminal and can result in problems. More particularly, when using a single DIO line, since the DIO line is always in the logic "high" state or the logic "low" state, when compared with the case of using the DIO lines in pairs, the read data transmitting pulse RDTP or the data transmission control pulse DTCP has to be enabled after sensing whether or not data of the DIO line is an effective value. If the read data transmitting pulse RDTP or the data transmission control pulse DTCP is enabled prior to the DIO line, non-effective data is provided to the DQ terminal upon reading and to the I/O lines upon writing. This results in generation of speed loss to ensure that effective data is obtained.
However, using pairs of DIO lines also has disadvantages. As the number of the I/O terminals increases, the number of the DIO lines within the chip is increased in proportion to the number of the I/O terminals, thereby causing the layout of the semiconductor memory device to be bulky. Therefore, when using DIO lines in pairs, this results in design problems due to spare occupied on the layout by the pairs of DIO lines.